Syllabus (COMPUTER SCIENCE)

Course Type: MAJ-3

Semester: 3

Course Code: BCOSMAJ03C

Course Title: Computer Organization and Computer Architecture

(L-P-Tu): 4-2-0

Credit: 6

Practical/Theory: Combined

Course Objective: • Understand the basic structure of Computer System, Instructions and Addressing Modes. • Understand the basic components, functions, and the design of CPU, ALU and Control Unit. • Study and analyze the model for pipelining. • Understand Memory Hi

Learning Outcome: • Understand the fundamental concepts and principles of computer organization and architecture. • Familiar with different instruction set architectures, such as CISC (Complex Instruction Set Computer) and RISC (Reduced Instruction Set Computer). • G

Theory

Digital Logic Circuits

Simplification, Fundamentals of Boolean Algebra, Combinational Circuits, Introduction to Sequential Circuits, Flip-Flops, Registers, Counters, Memory Units. (15 Lectures)

Data Representation and Basic Computer Arithmetic

Number Systems and Codes, Complements, Fixed and Floating-Point Representation, Character Representation, Addition, Subtraction, Multiplication and Division Algorithms for Integers. (10 Lectures)

Memory Organization

Memory system hierarchy, Main Memory Organization, Cache Memory, Virtual Memory. (15 Lectures)

Central Processing Unit

Register Organization, Instruction Set, Instruction Formats, Addressing Modes, Timing and Control, Instruction Cycle, Arithmetic and Logical Micro-operations, Stack Organization, Microprogrammed Control, RISC and CISC Architectures, Pipelining. (12 Lectures)

Input/ Output Organization

Introduction to computer buses, Bus control, I/O transfer techniques: Program controlled, Interrupt controlled and DMA, Interrupts. (8 Lectures)

Digital Electronics Lab

• Introduction to digital electronics lab- nomenclature of digital ICs, specifications, study of the data sheet, concept of Vcc and ground, verification of the truth tables of logic gates using TTL ICs.
• Implementation of Boolean functions using logic gates in both SOP and POS forms.
• Verification of state tables of RS, JK, T and D flip-flops using NAND & NOR gates.
• Implementation and verification of Multiplexer, De-multiplexer, Decoder, Encoder using logic gates.
• Implementation of 4x1 multiplexer using logic gates.
• Implementation of 4-bit parallel adder using 7483 IC.
• Design and verify 4-bit synchronous and asynchronous counter.

References:

1. William Stallings, Computer Organization and Architecture-Designing for Performance, Pearson Education.

2. M. Mano, Computer System Architecture, Pearson Education.

3. D. A. Patterson and J. L. Hennessy, Computer Organization and Design, Morgan Kaufmann.

4. V. C. Hamacher, Z. G. Veranesic, and S. G. Zaky, Computer Organization, Tata McGraw Hill.